A main focus of the contemporary semiconductor industry is the creation of smaller, faster, higher density, and more efficient memory modules. These efforts are often frustrated by cross talk and skew of signals being communicated on and to the memory modules, particularly as the memory modules become smaller. Cross talk is an inductive effect which can arise when a variable current flows through a conductor. Variable current creates a corresponding variable magnetic field surrounding the conductor capable of inducing a disruptive signal in any adjacent conductors passing through the magnetic field. As a consequence, the placement of conductors in a memory module must be carefully engineered in order to maintain suitable distances of separation between conductors to minimize the effects of cross talk.
Skew is a relatively fixed differential delay between two signals, commonly the result of the signals traveling different path lengths. One technique to eliminate skew is to make the path lengths along which signals are coupled the same length. In this way, signal travel time will be the same, thus eliminating any differential delay. Overall, the necessity of such careful considerations in both distancing conductors from each other and in creating equivalent path lengths to minimize the effects of cross talk and skew complicates efforts to produce effective memory modules with small dimensions.
Generally, memory modules are comprised of individual memory devices coupled in parallel on a circuit board. These memory devices can be dynamic random access memory (“DRAM”) devices suitable for a wide variety of applications. A partial top plan view of one type of memory module known in the art is shown in FIG. 1. As illustrated, two registered dual in-line memory modules (DIMM) 100a, 100b include a plurality of memory devices 102-116 arranged on a circuit board 140 and connected by a command/address bus 142 to a register 144. The memory devices 102-116 and the conductors of the command/address bus 142 are situated on the circuit board 140 with enough space between them to minimize any cross talk. The register 144 receives command signals applied through a control bus 146 and address signals applied through an address bus 148 from an external memory controller (not shown), such as what is typically referred to as a “north bridge controller” in a conventional computer system.
As illustrated in the registered memory module 100 shown in FIG. 1, the command signals applied to the register 144 include a row address strobe signal (“RAS#”) (the “#” indicates the signal is active low), a column address strobe signal (“CAS#”), clock enable signals (“CKE0” and “CKE7”), a write enable signal (“WE#”) and chip select signals (“CS0#”−“CS7#”) to activate the DRAM devices 102-116 on the respective memory modules 100a, 100b. Other signals not latched by the register 144 include a clock (“CK0”) signal, data signals (“DQ0-DQ63”) corresponding to a 64-bit data word applied to the modules through a data bus 150, and a number of other signals that are not pertinent to the present discussion. In the registered DIMMs 100a, 100b, bank address signals (“B0-B7”) corresponding to an 8-bit bank address and row/column address signals (“A0-A12”) corresponding to a 13-bit address are also applied to the register 144 through the address bus 148. Typically, groups of the DRAM devices 102-116 are coupled to respective chip select signals CS0#-CS7#, with each group receiving a given chip select signal being designated a “rank” of memory. In the following discussion, each DIMM 100a, 100b is assumed to include memory devices 102-116 on both sides of the DIMM, and groups of 4 memory devices (e.g., 102-108 and 110-116) are coupled to respective chip select signals CS0#-CS7# to define 4 ranks per DIMM. Each memory device 102-116 is thus a X16 device, meaning that each of the 4 memory devices in a given rank provides 16 of the 64 bit data bus DQ0-DQ63.
In operation, when a computer processor (not shown) reads data from, or writes data to, a specific memory address in a particular rank of memory device 102-116, it sends a signal to the memory controller (not shown) over a host bus (also not shown). The request is analyzed by the memory controller, which applies corresponding address signals A0-A12 and the previously described command signals to the registered DIMMs 100a-b. These signals are latched into the registers 144 of both of the DIMMs 100a-b, with the latched chip select signals CS0#-CS7# determining the rank of memory that is accessed. Only one chip select signal CS0#CS7# is activated to access the corresponding rank of memory on one of the DIMMs 100a-b. 
During write operations, the command signal includes address signals and command signals enabling the memory controller to access and write to a specific address in a respective rank of memory. Write data bits DQ0-DQ63 from the data bus 150 are then applied over an internal data path (not shown for the sake of clarity) on the DIMMs to the memory devices 102-116, and the memory devices in the active rank store the write data. The internal data path consists of individual traces running from the memory devices 102-116 to signal traces (not shown) on an edge of the circuit board 140. During write operations, the register 144 also operates to generate the appropriate command and timing signals to control the memory devices 102-116.
During read operations, the command signal includes address signals and command signals enabling the memory controller to access and read data from a specific address within the activated rank of memory. The read data stored in the active rank are then applied over the internal data path to the data bus 150 and, in turn, to the memory controller as read data bits DQ0-DQ64.
As can be seen in FIG. 1, the off-module command and address signals are applied to the midpoint of the module 100 such that the length of the control bus 146 and the address bus 148 on the module 100 are short. However, since the memory devices 102-116 are disposed on either side of the register 144, the path lengths of the command/address bus 142 to the memory devices 102-116 are of different lengths. As a result, address and command signals coupled from the register 144 to the different memory devices 102-116 are susceptible to skew. For example, the difference in delay in coupling command and address signals from the register 144 to the memory devices 102 and 108 makes it difficult to capture the command and address signals at both memory devices with a common clock signal. This potential for signal skew can seriously limit the operating speed of the memory devices 102-116.
One way to solve this problem is to increase the path lengths of the command/address bus 142 coupled to the memory devices 104-114 to make them equal to the path length of the command/address bus 142 to the devices 102 and 116. While such a solution is effective in alleviating skew, it requires the placement of a greater length of conductive lines on the DIMMs 100a, 100b. This consumes more space, increases propagation delay, and may adversely affect signal integrity. Further, as memory bus speeds continue to increase, a need will arise to buffer data signals along with the command address signals such that a data buffer will be included on each memory module 100a, 100b to perform a similar function for data signals as the register 144 does for command and address signals.
A new computer memory architecture currently being developed is known as a memory hub architecture. In a memory hub architecture, a system controller or memory controller is coupled over a high-speed data link, such as a fiber optic link, to several memory modules. The memory modules are typically coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Each memory module includes a memory hub that is coupled to the corresponding high-speed data links and is also coupled to a number of memory devices on the module. The memory hubs efficiently route memory requests and responses between the controller and the memory devices via the high-speed data links. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device or rank of memory while another memory device or rank is responding to a prior memory access. For example, the processor can output write data to one rank of memory in the system while another rank is preparing to provide read data to the processor.
The command, address, and data signals between each memory hub and the corresponding memory devices can experience cross talk and skew just as do the signals on conventional memory modules as previously discussed. To increase the overall bandwidth of a memory utilizing the memory hub architecture, the signals between the hub and memory devices are very high-speed, which only exacerbates the problems created by any skew due to the more restrictive timing requirements, as will be understood by those skilled in the art. If each memory module has a layout like the DIMMs 100a, 100b of FIG. 1, layout and routing congestion problems arise. With the memory hub being positioned in the center of the circuit board 140 in place of the register 144 and the DRAMs 102-116 positioned as shown, the skew of signals to and from each DRAM 102-116 is different.
This skew presents timing problems for the memory hub, particularly with regard to read data from the DRAMs which will arrive at the hub at different times yet must be accurately captured. The hub could execute a synchronization process for each DRAM, but this would increase the complexity and cost of the memory hub. Routing congestion problems also arise with this layout due to all the signals that must be routed between the devices and the hub. While more layers could be added to the circuit board 140, this increases the complexity and cost of the board.
There is a need for a memory module that minimizes skew and maximizes signal integrity between a memory hub and memory devices as well as between the module and a memory controller.